View IDT77V106L25TFI_5881359.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 may 2004 idt77v106l25 3.3v atm phy for 25.6 and 51.2 mbps ? 2004 integrated device technology, inc. all rights reserved. product specifications subject to change without notice dsc-5360/4 idt and the idt logo are registered trademarks of integrated device technology, inc. features: ? ? ? ? ? performs the phy-transmission convergence (tc) and physical media dependent (pmd) sublayer functions of the physical layer ? ? ? ? ? compliant to atm forum (af-phy-040.000) and itu-t i.432.5 specifications for 25.6mbps physical interface ? ? ? ? ? also operates at 51.2mbps data rate ? ? ? ? ? 8-bit utopia level 1 interface ? ? ? ? ? 3-cell transmit & receive fifos ? ? ? ? ? receiver auto-synchronization and good signal indication ? ? ? ? ? led interface for status signalling ? ? ? ? ? supports utp category 3 and 5 physical media ? ? ? ? ? interfaces to standard magnetics ? ? ? ? ? low-power cmos ? ? ? ? ? 3.3v supply with 5v tolerant inputs ? ? ? ? ? 64-lead tqfp package (10 x 10 mm) ? ? ? ? ? commercial and industrial temperature ranges description: the idt77v106l25 is a member of idt?s family of products supporting asynchronous transfer mode (atm) data communications and networking. the idt77v106l25 implements the physical layer for 25.6 mbps atm, connecting a serial copper link (utp category 3 and 5) to an atm layer device such as a sar or a switch asic. the idt77v106l25 also operates at 51.2 mbps and is well suited to back-plane driving applications. the 77v106l25 utilizes an 8-bit utopia interface on the cell side. the idt77v106l25 is fabricated using idt?s state-of-the-art cmos technology, providing the highest levels of integration, performance and reliability, with the low-power consumption characteristics of cmos. applications: ? ? ? ? ? up to 51.2mbps backplane transmission ? ? ? ? ? rack-to-rack short links ? ? ? ? ? atm switches block diagram txref txdata txsoc txen ale rxclav wr rd cs ad[7:0] int rxdata rxsoc rxen txclav rxref 3 cell fifo 9 8 9 utility bus controller 3 cell fifo scrambler prng descrambler 5b/4b decoder s/p dnrzi 4b/5b encoder p/s nrzi clk rec txd+ line driver txd- line rxvr rxd+ rxd- loop back reset rxled osc 77v106 77v106 drw 01 txled reset txclk rxclk
2 idt77v106l25 77v106l25 overview the 77v106l25 is a physical layer interface chip for 25.6mbps atm network communications as defined by atm forum document af-phy-040.000 and itu-t i.432.5. the physical layer is divided into a physical media dependent sub layer (pmd) and transmission convergence (tc) sub layer. the pmd sub layer includes the functions for the transmitter, receiver and clock recovery for operation across 100 meters of category 3 and 5 unshielded twisted pair (utp) cable. this is referred to as the line side interface. the tc sub layer defines the line coding, scrambling, data framing and synchronization. on the cell side, the 77v106l25 connects to an atm layer device (such as a switch core or sar) through an 8-bit utopia level 1 interface. the 77v106l25 is based on the 77105 and maintains significant register compatibility with it, but it also has additional register features. access to these status and control registers is through the utility bus. this is an 8-bit muxed address and data bus, controlled by a conventional asynchronous read/write handshake. additional pins permit insertion and extraction of an 8khz timing marker, and provide led indication of receive and transmit status. operation at 51.2 mbps in addition to operation at the standard rate of 25.6 mbps, the 77v106l25 is also specified to operate at 51.2 mbps. except for the doubled bit rate, all other aspects of operation are identical to the 25.6 mbps mode. the rate is determined by the frequency of the clock applied to the osc input pin. osc is 32 mhz for the 25.6 mbps line rate, and 64 mhz for the 51.2 mbps line rate. see figure 16 for recommended line magnetics. magnetics for 51.2 mbps operation have a higher bandwidth than magnetics optimized for 25.6 mbps. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 rxref txref txled txdata0 txdata1 txdata2 txdata3 txdata4 txdata5 txdata6 txdata7 txen txsoc vdd txclav txclk rxen rxclav rxsoc gnd rxparity rxdata7 rxdata6 rxdata5 rxdata4 vdd rxdata3 rxdata2 rxdata1 rxdata0 17 18 19 21 22 23 24 25 26 27 28 29 30 32 20 31 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 ad7 ad6 ad5 ad4 gnd ad3 ad2 ad1 ad0 ale cs rd wr rst int rxled 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 se agnd avdd osc agnd avdd agnd avdd rxd- rxd+ avdd gnd txd- txd+ sm 77v106 drw 02 rxclk txparity vdd pin 1 index idt77v106 figure 1. pin assignments
3 idt77v106l25 line side signals signal name pin number i/o signal description rxd+, rxd- 58, 57 in positive and negative receive differential input pair. txd+, txd- 62, 61 out positive and negative transmit differential output pair. utility bus signals signal name pin number i/o signal description ad[7:0] 48, 47, 46, in/ utility bus address/data bus. the address input is sampled on the falling edge of ale. data is output on 45, 43, 42, out this bus when a read is performed. input data is sampled at the completion of a write operation. 41, 40. ale 39 in utility bus address latch enable. asynchronous input. an address on the ad bus is sampled on the falling edge of ale. ale must be low when the ad bus is being used for data. cs 38 in utility bus asynchronous chip select. cs must be asserted to read or write an internal register. it may remain asserted at all times if desired. rd 37 in utility bus read enable. active low asynchronous input. after latching an address, a read is performed by deasserting wr and asserting rd and cs . wr 36 in utility bus write enable. active low asynchronous input. after latching an address, a write is performed by deasserting rd , placing data on the ad bus, and asserting wr and cs . data is sampled when wr or cs is deasserted. utopia bus signals signal name pin number i/o signal description rxclav 20 out utopia receive cell available. "1" indicates that the receive fifo contains a complete cell. "0" indicates that it does not. rxclk 18 in utopia receive clock. this is a free running clock input. rxdata[7:0] 24, 25, 26, out utopia receive data. when one of the four ports is selected, the 77v106l25 transfers received cells t o 27, 29, 30 an atm device across the bus. also see rxparity. 31, 32. rxen 19 in utopia receive enable. driven by an atm device to indicate its ability to receive data across the rxdata bus. rxparity 23 out utopia receive data parity. odd parity over rxdata[7:0]. rxsoc 21 out utopia receive start of cell. asserted coincident with the first word of data for each cell on rxdata. txclav 16 out utopia transmit cell available. "1" indicates that the transmit fifo has room available for at least one complete cell. "0" indicates that it does not. txclk 17 in utopia transmit clock. this is a free running clock input. txdata[7:0] 11, 10, 9, 8 in utopia transmit data. an atm device transfer cell across this bus to the 77v106l25 for transmission. also 7, 6, 5, 4 see txparity. txen 13 in utopia transmit enable. driven by an atm device to indicate it is transmitting data across the txdata bus. txparity 12 in utopia transmit data parity. odd parity across txdata[7:0]. parity is checked and errors are indicated in the interrupt status registers, as enabled in the master control register. no other action is taken in the even of an error. tie high or low if unused. txsoc 14 in utopia transmit start of cell. asserted coincident with the first word the first word of data for each cell on txdata. table 1 signal description (part 1 of 2)
4 idt77v106l25 miscellaneous signals signal name pin number i/o signal description int 34 out interrupt int is an open-drain output, driven low to indicate an interrupt. once low, int remains low until the interrupt status in the appropriate interrupt status register is read. interrupt sources are programmable via the interrupt mast registers. osc 52 in ttl line rate clock source, driven by a 100 ppm oscillator. 32mhz for 25.63 mbps; 65 mhz for 51.2 mbps. rst 35 in reset. active low asynchronous input resets all control logic, counters and fifos. a reset must be performed after power up prior to normal operation of the part. rxled 33 out receive led driver. driven low for 223 cycles of osc, beginning with rxsoc when a good (non-null and non-errored) cell is received. drives 8 ma both high and low. rxref 1 out receive reference. active low. rxref pulses low for a programmable number of clock cycles when an x_8 command byte is received. se 49 in reserved signal. this input must be connected to logic low. sm 64 in reserved signal. this input must be connected to logic low. txled 3 out transmit led driver. goes low for 223 cycles of osc, beginning with txsoc when a cell is received for transmission. 8 ma drive current both high and low. txref 2 in transmit reference. at the falling edge of txref , an x_8 command byte is inserted into the transmit data stream. typical application is wan timing. table 1 signal description (part 2 of 2) power supply signals signal name pin number i/o signal description agnd 50, 53, 55 ? analog ground. agnd is ground the analog portion of the ship, which sources a more constant current than the digital portion. avdd 51, 54, 56 ? analog power supply. avdd supplies power to the analog portion of the chip, which draws a more constant 59 current than the digital portion. 3.3 0.34v gnd 22, 44, 60 ? digital ground. vdd 15, 28,63 ? digital power supply. 3.3 0.3v
5 idt77v106l25 functional description transmission convergence (tc) sub layer introduction the tc sub layer defines the line coding, scrambling, data framing and synchronization. under control of a switch interface or segmentation and reassembly (sar) unit, the 25.6mbps atm phy accepts a 53-byte atm cell, scrambles the data, appends a command byte to the beginning of the cell, and encodes the entire 53 bytes before transmission. these data transformations ensure that the signal is evenly distributed across the frequency spectrum. in addition, the serialized bit stream is nrzi coded. an 8khz timing sync pulse may be used for isochronous communications. data structure and framing each 53-byte atm cell is preceded with a command byte. this byte is distinguished by an escape symbol followed by one of 17 encoded symbols. together, this byte forms one of seventeen possible command bytes. three command bytes are defined: 1. x_x (read: ?escape? symbol followed by another ?escape?): start-of- cell with scrambler/descrambler reset. 2. x_4 (?escape? followed by ?4?): start-of-cell without scrambler/ descrambler reset. 3. x_8 (?escape? followed by ?8?): 8khz timing marker. this command byte is generated when the 8khz sync pulse is detected, and has priority over all line activity (data or command bytes). it is transmitted immediately when the sync pulse is detected. when this occurs during a cell transmission, the data transfer is temporarily interrupted on an octet boundary, and the x_8 command byte is inserted. this condition is the only allowed interrupt in an otherwise contiguous transfer. below is an illustration of the cell structure and command byte usage: {x_x} {53-byte atm cell} {x_4} {53-byte atm {x_8} cell}... in the above example, the first atm cell is preceded by the x_x start-of- cell command byte which resets both the transmitter-scrambler and receiver- descrambler pseudo-random nibble generators (prng) to their initial states. the following cell illustrates the insertion of a start-of-cell command without scrambler/descrambler reset. during this cell?s transmission, an 8khz timing sync pulse triggers insertion of the x_8 8khz timing marker command byte. transmission description refer to figure 2. cell transmission begins with the phy-atm interface. an atm layer device transfers a cell into the 77v106l25 across the utopia transmit bus. this cell enters a 3-cell deep transmit fifo. once a complete cell is in the fifo, transmission begins by passing the cell, four bits (msb first) at a time to the ?scrambler?. the ?scrambler? takes each nibble of data and exclusive-ors them against the 4 high order bits (x(t), x(t-1), x(t-3)) of a 10 bit pseudo-random nibble generator (pring). its function is to provide the appropriate frequency distribution for the signal across the line. the prng is clocked every time a nibble is processed, regardless of whether the processed nibble is part of a data or command byte. note however that only data nibbles are scrambled. the entire command byte (x _c) is not scrambled before it?s encoded (see diagram for illustration). the prng is based upon the following polynomial: x 10 + x 7 + 1 with this polynomial, the four output data bits (d3, d2, d1, d0) will be generated from the following equations: d3 = d3 xor x(t-3) d2 = d2 xor x(t-2) d1 = d1 xor x(t-1) d0 = d0 xor x(t) the following nibble is scrambled with x(t+4), x(t+3), x(t+2), and x(t+1). a scrambler lock between the transmitter and receiver occurs each time an x_x command is sent. an x_x command is initiated only at the beginning of a cell transfer after the prng has cycled through all of its states (2 10 - 1 = 1023 states). the first valid atm data cell transmitted after power on will also be accompanied with an x_x command byte. each time an x_x command byte is sent, the first nibble after the last escape (x) nibble is xor?d with 1111b (prng = 3ffx). because a timing marker command (x_8) may occur at any time, the possibility of a reset prng start-of-cell command and a timing marker command occurring consecutively does exist (e.g. x_x_x_8). in this case, the detection of the last two consecutive escape (x) nibbles will cause the prng to reset to its initial 3ffx state. therefore, the prng is clocked only after the first nibble of the second consecutive escape pair. once the data nibbles have been scrambled using the prng, the nibbles are further encoded using a 4b/5b process. the 4b/5b scheme ensures that an appropriate number of signal transitions occur on the line. a total of seventeen 5-bit symbols are used to represent the sixteen 4-bit data nibbles and the one escape (x) nibble. the table below lists the 4-bit data with their corresponding 5-bit symbols: data 0000 0100 1000 1100 symbol 10101 00111 10010 10111 symbol 01001 01101 11001 11101 data 0001 0101 1001 1101 symbol 01010 01110 11010 11110 data 0010 0110 1010 1110 data 0011 0111 1011 1111 esc(x) = 00010 3505 drw 05a symbol 01011 01111 11011 11111
6 idt77v106l25 phy-atm interface control, hec gen. & insertion scrambler 4 command byte insertion 4 prng 4 scramble nibble next reset 4b/5b encoding 4 nrzi encoding 1 tx + tx - 32mhz 64mhz clock input txref (8khz) 3505 drw 05 3 cells start of cell utopia interface figure 2. tc transmit block diagram
7 idt77v106l25 this encode/decode implementation has several very desirable properties. among them is the fact that the output data bits can be represented by a set of relatively simple symbols; run length is limited to <= 5; disparity never exceeds +/- 1. on the receiver, the decoder determines from the received symbols whether a timing marker command (x_8) or a start-of-cell command was sent (x_x or x_4). if a start-of-cell command is detected, the next 53 bytes received are decoded and forwarded to the descrambler. (see the tc receive block diagram). the output of the 4b/5b encoder provides serial data to the nrzi encoder. the nrzi code transitions the wire voltage each time a ?1? bit is sent. this, together with the previous encoding schemes guarantees that long run lengths of either ?0? or ?1?s are prevented. each symbol is shifted out with its most significant bit sent first. when no cells are available to transmit, the 77v106l25 keeps the line active by continuing to transmit valid symbols. but it does not transmit another start-of-cell command until it has another cell for transmission. the 77v106l25 never generates idle cells. transmit hec byte calculation/insertion byte #5 of each atm cell, the hec (header error control) is calculated automatically across the first 4 bytes of the cell header, depending upon the setting of bit 5 of the led driver and hec status/control register (0x03). this byte is then either inserted as a replacement of the fifth byte transferred to the phy by the external system, or the cell is transmitted as received. a third operating mode provides for insertion of ?bad? hec codes which may aid in communication diagnostics. these modes are controlled by the led driver and hec status/control registers. receiver description the receiver side of the tc sublayer operates like the transmitter, but in reverse. the data is nrzi decoded before each symbol is reassembled. the symbols are then sent to the 5b/4b decoder, followed by the command byte interpreter, de-scrambler, and finally through a fifo to the utopia interface to an atm layer device. atm cell format note that although the idt77v106l25 can detect symbol and hec errors, it does not attempt to correct them good signal bit: upon resetting the device or reestablishing a serial link, logic in front of the 4b/5b decoder uses feedback from the 4b/ 5b decoder to determine if it is not properly ?framed? on the 5-bit symbols being received. if not properly framed, it will shift its framing, one bit at a time, until it achieves proper symbol framing. receipt of an escape (x) symbol will also force proper symbol framing. the idt77v106l25 monitors line conditions and can provide an interrupt if the line is deemed ?bad?. the interrupt status register contains a good signal bit (bit 6, set to 0 = bad signal initially) which shows the status of the line per the following algorithm: to declare ?good signal? (from ?bad? to ?good?) there is an up-down counter that counts from 7 to 0 and is initially set to 7. when the clock ticks for 1,024 cycles (32mhz clock, 1,024 cycles = 204.8 symbols) and no ?bad symbol? has been received, the counter decreases by one. however, if at least one ?bad symbol? is detected during these 1,024 clocks, the counter is increased by one, to a maximum of 7. the good signal bit is set to 1 when this counter reaches 0. the good signal bit could be set to 1 as quickly as 1,433 symbols (204.8 x 7) if no bad symbols have been received . to declare ?bad signal? (from ?good? to ?bad?) the same up-down counter counts from 0 to 7 (being at 0 to provide a ?good? status). when the clock ticks for 1,024 cycles (32mhz clock, 1,024 cycles = 204.8 symbols) and there is at least one ?bad symbol?, the counter increases by one. if it detects all ?good symbols? and no ?bad symbols? in the next time period, the counter decreases by one. the ?bad signal? is declared when the counter reaches 7. the good signal bit could be set to 0 as quickly as 1,433 symbols (204.8 x 7) if at least one ?bad symbol? is detected in each of seven consecutive groups of 204.8 symbols. 8khz timing marker the 8khz timing marker, described earlier, is a completely optional feature which is essential for some applications requiring synchronization for voice or video, and unnecessary for other applications. when unused, txref should be tied high. also note that it is not limited to 8khz, should a different frequency be desired. when looped, a received x_8 command byte causes one to be generated on the transmit side. a received x_8 command byte causes the 77v106l25 to issue a negative pulse on rxref . bit 7 bit 0 header byte 1 header byte 2 header byte 3 header byte 4 udf payload byte 1 ? ? ? payload byte 48 3505 drw 52 udf = user defined field (or hec)
8 idt77v106l25 phy-atm interface utopia level 1 is a physical (phy) layer to atm layer interface standardized by the atm forum. it is used for transferring atm cells and has separate transmit and receive channels and specific handshaking protocols. it is defined in atm forum documents af-phy-0017 and af-phy-0039. 4 phy-atm interface control - recv 4 5 nrzi decoding rx + rx 4 4 prng scramble nibble next reset rxref 32.0mhz clock synthesizer & pll 5b/4b decoding command byte detection, removal, & decode de- scrambler 3505 drw 06 osc 3 cells start of cell utopia interface the utopia signals are summarized below: txdata[7:0] atm to phy txparity atm to phy txsoc atm to phy txen atm to phy txclav phy to atm txclk atm to phy rxdata[7:0] phy to atm rxparity phy to atm rxsoc phy to atm rxen atm to phy rxclav phy to atm rxclk atm to phy transmit and receive both utilize free running clocks, which are inputs to the 77v106. all utopia signals are timed to these c locks. figure 3. receive block diagram there is a single 8-bit data bus in the transmit (atm-to-phy) direction, and a single 8-bit data bus in the receive (phy-to-atm) direction. in addition to the data bus, each direction also includes a single optional parity bit and several handshaking signals. please note that the transmit bus and the receive bus operate completely independently.
9 idt77v106l25 in the transmit direction, the phy first asserts txclav (transmit cell available) to indicate that it has room in its transmit fifo to accept at least one 53-byte atm cell. when the atm layer device is ready to begin passing the cell, it asserts txen (transmit enable) and txsoc (start of cell), coincident with the first byte of the cell on txdata. txen can remain asserted for the duration of the cell transfer, or the atm device may deassert txen at any time once the cell transfer has begun; data is transferred only when txen is asserted. in the receive direction, rxen indicates when the atm device is prepared to receive data. as with transmit, it may be asserted or deasserted at any time. note that this utopia interface can be operated in either cell-mode or in byte- mode as determined by bit 1 in the master control register. in cell-mode, which is the default, the 77v106l25 does not assert txclav until it has enough room in it?s transmit fifo to accept a complete cell, and doesn?t assert rxclav until it has a complete cell in the receive fifo. it will not deassert txclav or rxclav until at or near the end of the transfer of a cell. txclk txsoc txclav txen txdata[7:0], txparity x h1 h2 p44 p45 p46 p47 p48 x 77v106 drw 16 txclk txsoc txclav txen txdata[7:0], txparity p46 p47 p48 h1 h2 h3 h4 x h5 77v106 drw 17 figure 4. utopia transmit handshake - single cell figure 5. utopia transmit handshake - back to back cells and txen suspended transmission in byte-mode, the phy can assert txclav before it has room for a complete cell. it will modulate txclav to prevent the fifo from overflowing. likewise, it may assert rxclav before a complete cell has been received, and will modulate rxclav to prevent the fifo from underflowing. there is generally little advantage to the byte-mode, so most users will leave the 77v106l25 in the default cell-mode. in both transmit and receive, txsoc and rxsoc (start of cell) is asserted for one clock, coincident with the first byte of each cell. odd parity is utilized across each 8-bit data field, which means that for an all-zero pattern. the corresponding parity bit is one. the following figures show examples of the utopia level 1 handshake.
10 idt77v106l25 txclk txsoc txclav txen txdata[7:0], txparity p42 p43 p44 p45 p46 x x x p47 77v106 drw 18 p48 h1 figure 6. utopia transmit handshake - txen suspended transmission and back to back cells (octet mode only) txclk txsoc txclav txen txdata[7:0], txparity h1 h2 h3 77v106 drw 19 p48 p47 high-z high-z figure 7. utopia transmit handshake - delay between cells rxclk rxsoc rxclav rxen rxdata[7:0], rxparity h1 p47 p48 77v106 drw 20 p48 p47 high-z high-z x x h1 h2 figure 8. utopia receive handshake - rxen and rxclav control rxclk rxsoc rxclav rxen rxdata[7:0], rxparity p48 x 77v106 drw 21 p44 p42 high-z high-z p43 p45 p46 p47 high-z high-z x early rxclav option (bit 6=1, register 0x02) figure 9. utopia receive handshake - rxclave deassertion
11 idt77v106l25 control and status interface utility bus the utility bus is a byte-wide interface that provides access to the registers within the idt77v106. these registers are used to select desired operating characteristics and functions, and to communicate status to external systems. the utility bus is implemented using a multiplexed address and data bus (ad[7:0]) where the register address is latched via the address latch enable (ale) signal. the utility bus interface is comprised of the following pins: ad[7:0], ale, cs, rd, wr read operation refer to the utility bus timing waveforms. a register read is performed as follows: 1. initial condition: ? rd , wr , cs not asserted (logic 1) ? ale not asserted (logic 0) 2. set up register address: ? place desired register address on ad[7:0] ? set ale to logic 1; ? latch this address by setting ale to logic 0. 3. read register data: ? remove register address data from ad[7:0] ? assert cs by setting to logic 0; ? assert rd by setting to logic 0 ? wait minimum pulse width time (see ac specifications) write operation a register write is performed as described below: 1. initial condition: ? rd , wr , cs not asserted (logic 1) ? ale not asserted (logic 0) 2. set up register address: ? place desired register address on ad[7:0] ? set ale to logic 1; ? latch this address by setting ale to logic 0. 3. write data: ? place data on ad[7:0] ? assert cs by setting to logic 0; ? assert wr (logic 0) for minimum time (according to timing specification); reset wr or cs to logic 1 to complete register write cycle. interrupt operations a variety of selectable interrupt and signalling conditions are provided. they are useful both during ?normal? operation, and as diagnostic aids. refer to the status and control register list section. overall interrupt control is provided via bit 0 of the master control register. when this bit is cleared (set to 0), interrupt signalling is prevented. the interrupt mask register allows individual masking of different interrupt sources. additional interrupt signal control is provided by bit 5 of the master control register. when this bit is set (=1), receive cell errors will be flagged via interrupt signalling and all other interrupt conditions are masked. these errors include: ? bad receive hec ? short (fewer than 53 bytes) cells ? received cell symbol error normal interrupt operations are performed by setting bit 0 and clearing bit 5 in the master control register. int (pin 34) will go to a low state when an interrupt condition is detected. the external system should then interrogate the 77v106l25 to determine which one (or more) conditions caused this flag, and reset the interrupt for further occurrences. this is accomplished by reading the interrupt status register. decoding the bits in this byte will tell which error condition caused the interrupt. reading this register also: ? clears the (sticky) interrupt status bits in the registers that are read ? resets int this leaves the interrupt system ready to signal an alarm for further problems.
12 idt77v106l25 state pin voltage cells being received low cells not being received high as illustrated in figure 11, this could be connected to provide for a two- led condition indicator. rxclk rxsoc rxclav rxen rxdata[7:0], rxparity h1 h2 x 77v106 drw 22 high-z high-z h3 h4 h5 p1 figure 10. utopia receive handshake - rxclav suspended transfer (octet mode only) txled truth table state pin voltage cells being transmitted low cells not being transmitted high diagnostic functions rxled txled 3.3v (indicates: cells being received or transmitted) (indicates: cells are not being received or transmitted) 3505 drw 32 r r figure 11. led indicator led control and signaling the led outputs provide bi-directional led drive capability of 8 ma. as an example, the rxled outputs are described in the truth table: these could also be different colors to provide simple status indication at a glance. (the minimum value for r should be 330 ? ).
13 idt77v106l25 bit 1 bit 2 mode 0 0 normal operating mode 1 0 phy loopback 1 1 line loopback normal mode figure 12 shows normal operating conditions: data to be transmitted is transferred to the tc, where it is queued and formatted for transmission by the pmd. receive data from the pmd is decoded along with its clock for transfer to the receiving "upstream system". phy loopback as figure 13 illustrates below, this loopback mode provides a connection within the phy from the transmit phy-atm interface to the phy-atm receive interface. note that while this mode is operating, no data is forwarded to or received from the line interface. loopback there are two loopback modes supported by the 77v106. the loopback mode is controlled via bits 1 and 0 of the diagnostic control register. line loopback figure 14 might also be called "remote loopback" since it provides for a means to test the overall system, including the line. since this mode will probably be entered under direction from another system (at a remote location), receive data is also decoded and transferred to the upstream system to allow it to listen commands. a common example would be command asking the upstream system to direct the tc to leave this loopback state and resume normal operations. figure 13. phy loopback figure 14. line loopback tc sublayer pmd sublayer line interface atm layer device 77v106 drw 33 utopia interface figure 12. normal mode atm layer device tc sublayer pmd sublayer line interface 77v106 drw 34 utopia interface atm layer device tc sublayer pmd sublayer line interface 77v106 drw 35 utopia interface
14 idt77v106l25 counters several condition counters are provided to assist external systems (e.g. software drivers) in evaluating communications conditions. it is anticipated that these counters will be polled from time to time (user selectable) to evaluate performance. ? symbol error counters ? 8 bits ? counts all invalid 5-bit symbols received ? transmit cell counters ? 16 bits ? counts all transmitted cells ? receive cell counters ? 16 bits ? counts all received cells, excluding idle cells and hec errored cells ? receive hec error counters ? 5 bits ? counts all hec errors received the txcell and rxcell counters are sized (16 bits) to provide a full cell count (without roll over) if the counter is read once/second. the symbol error counter and hec error counter were given sufficient size to indicate exact counts for low error-rate conditions. if these counters overflow, a gross condition is occurring, where additional counter resolution does not provide additional diagnostic benefit. reading counters 1. decide which counter value is desired. write to the counter select register to the bit location corresponding to the desired counter. this loads the high and low byte counter registers with the selected counter?s value, and resets this counter to zero. note :only one counter may be enabled at any time in each of the counter select registers. 2. read the counter registers (low byte and high byte) to get the value. further reads may be accomplished in the same manner by writing to the counter select registers. note: the phy takes some time to set up the low and high byte counters after a specific counter has been selected in the counter selector register. this time delay (in s) varies with the line rate and can be calculated as follows: time delay (s) = 12.5___ line rate (mbps) loop timing feature the 77v106l25 also offers a loop timing feature for specific applications where data needs to be repeated / transmitted using the recovered clock. if the loop timing mode is enabled in the enhanced control register 1 bit 6, the recovered receive clock is used as to clock out data on transmit side. in normal mode, the transmitter transmits data using the multiplied oscillator clock. jitter in loop timing mode one of the primary concerns when using loop timing mode is the amount of jitter that gets added each time data is transmitted. table 2 shows the jitter measured at various data rates. the set-up shown in figure 15 was used to perform these tests. the maximum jitter seen was at tx point 5 and the minimum jitter was at point 2. the loop timing jitter is defined as the amount of jitter generated by each tx node. in other words, the loop timing jitter or the jitter added by a loop-timed port in the set-up below is the difference between the total output jitter and the total input jitter.
15 idt77v106l25 data data data data data data sw itch loop timing mode loop timing mode loop timing mode line card 2 line card 3 line card 4 clk clk clk rx rx rx tx tx tx tx rx normal mode line card 1 os c 1 2 3 4 5 figure 15 figure 15. test setup for loop timing jitter measurements loop timing jitter specification line rate data rate min. typ. max. note mbps mbps 32 25.6 ? 100 ps ? using 32mhz osc 64 51.2 ? 100 ps ? using 64mhz osc the waveforms below show some of the measurements taken with the set- up in figure 15. using the formula above, the jitter specification was derived. table 2 loop timing jitter for example, at data rate 25.63 mbps, jitter added going through line card 3 is 1.5ns - 1.4ns (as shown in the waveform below).
16 idt77v106l25 jitter at 25.6mbps at point 4 with respect to point 1 jitter at 25.6mbps at point 5 with respect to point 1 jitter at 51.2mbps at point 4 with respect to point 1 jitter at 51.2mbps at point 5 with respect to point 1 from the above measurements taken, the amount of jitter being added at each tx point is not significant. these tests were also run for extended periods of time (64 hours) and no bit error were seen.
17 idt77v106l25 7 8 10 9 345 magnetics rj45 connector idt77v106 agnd 14 13 12 agnd 1 2 16 15 agnd avdd rxd+ rxd- txd+ txd- r1 r2 r3 r4 r5 r8 r9 r7 c1 c2 l1 77v106 drw 36 r6 1 2 3 4 5 6 7 8 . figure 16. recommended connection to magnetics line side (serial) interface phy to magnetics interface a standard connection to 100 ? and 120 ? unshielded twisted pair cabling is shown in figure 16. note that the transmit signal is somewhat attenuated in order to meet the launch amplitude specified by the standards. the external receive circuitry is designed to attenuate low frequencies in order to compensate for the high frequency attenuation of the cable. also, the receive circuitry biases the positive and negative rx inputs to slightly different voltages. this is done so that the receiver does not receive false signals in the absence of a real signal. this can be important because the 77v106l25 does not disable error detection or interrupts when an input signal is not present. when connecting to utp at 51.2 mbps, it is necessary to use magnetics with sufficient bandwidth. refer to table 4 for the recommended magnetics.
18 idt77v106l25 status and control register list master control register address: 0x00 bit type initial state function 7 r/w 0 = osc clock multiplier. controls whether or not the osc reference clock inputs is multiplied by two to generate the line multiplied by clock. one cleared (0) = osc is multiplied by 1 to generate line clock set (1) = osc is multiplied by 2 to generate line clock 6 r/w 1 = discard discard receive error cell s errored on receipt of any cell with an error (e.g. short cell, invalid command mnemonic, receive hec error (if cells enabled), this cell will be discarded and will not enter the receive fifo. 5 r/w 0 = all interrupts enable cell error interrupts only if bit 0 in this register is set (interrupts enabled), setting of this bit enables only "received cell error" (as defined in bit 6) to trigger interrupt line". 4 r/w 0 = disabled transmit data parity cells directs tc to check parity of txdata against parity bit located in txparity. 3 r/w 1 = discard discard received idle cells idle cells directs tc to discard received idle (vpi/vci = 0 and gfc = 0) cells from pmd without signaling external systems. 2 r/w 0 = not halted halt tx halts transmission of data from tc to pmd and forces the txd output to the "0" state. 1 r/w 0 = cell mode utopia mode select 0 = cell mode, 1 = byte mode. 0 r/w 1 = enable enable interrupt pin (interrupt mask bit) interrupts enables the int output pin. if cleared, pin is always high and interrupt is masked. if set, an interrupt will be signaled by setting the interrupt pin to "0". it doesn't affect the interrupt status registers". nomenclature "reserved" register bits, if written, should always be written "0" r/w = register may be read and written via the utility bus r-only or w-only = register is read-only or write only sticky = register bit is cleared after the register containing it is read; all sticky bits are read-only "0" = "cleared" or "not set" "1" = "set" table 3 analog component values note: 1) the recommended pull up/pull down for r5 and r6 or 10k ? resistors. this is not an absolute value and it can be changed if necessary. table 4 magnetics modules magnetics modules for 25.6 mbps pulse pe-67583 or r4005 www.pulseeng.com tdk tla-6m103 www.component.tdk.com magnetics modules for 51.2 mbps pulse r4005 www.pulseeng.com component value tolerance r1 47 ? 5% r2 47 ? 5% r3 620 ? 5% r4 110 ? 5% r5 (1) 10k ? 5% r6 (1) 10k ? 5% r7 82 ? 5% r8 33 ? 5% r9 33 ? 5% c1 470pf ? 20% c2 470pf ? 20% l1 3.3 h 20%
19 idt77v106l25 interrupt status register address: 0x01 7- 0 reserved 6 r 0 = bad signal good signal bit . see definitions earlier in this data sheet 1 - good signal 1 - bad signal 5 sticky 0 hec error cell received. set when a hec errors detected on received cell. 4 sticky 0 "short cel" received interrupt signal which flags received cells with fewer than 53 bytes. this condition is detected when receiving start-of-cell command bytes with fewer than 53 bytes between them" 3 sticky 0 transmit parity error if bit 4 of the master control register (transmit data parity check) is set, this interrupt flags a transmit data parity error condition. odd parity is used. 2 sticky 0 receive signal condition change . this interrupt is set when the received "signal" changes either from "bad to good" from "good to bad". 1 sticky 0 received symbol error. set when an undefined 5-bit symbol is received. 0 sticky 0 receive fifo overflow. interrupt which indicates when the receive fifo has filled and cannot accept additional data. bit type initial state function diagnostic control register address: 0x02 bit type initial state function 7 r/w 0 = normal force txclav deassert this feature can be used during line loopback mode to prevent cells from being passed across the utopia bus for transmission. 6 r/w 0 = utopia rxclav operation select the utopia standard dictates that during cell mode operation, if the receive fifo no longer has a complete cell available for transfer from phy, rxclav is deasserted following transfer of the last byte out of the phy to the upstream system. with this bit set, early deassertion of this signal will occur coincident with the end of payload byte 44 (as in octet mode for txclav). this provides early indication to the upstream system of this impending condition. 0 = "standard utopia rxclav" 1 = "cell mode = byte mode" 5 r/w 0 = high-z single/multi-phy configuration select 0 = single never high-z rxday+ta, rxparity, and rxsoc 1 = multi-phy mode high-z rxdata, rxparity, and rxsoc when rxen = 1 4 r/w 0 = normal rflush = clear receive fifo this signal is used to tell the tc to flush (clear) all data in the receive fifo. the tc signals this completion by clearing this bit. 3 r/w 0 = normal insert transmit payload error tells tc to insert cell payload errors in transmitted cells. this can be used to test error detection and recovery systems at destination station, or, under loopback control, at the local receiving station. this payload error is accomplished by flipping bit 0 of the last cell payload byte. 2 r/w 0 = normal insert transmit hec error tells tc to insert hec error in byte 5 of transmitted cells. this can be used to test error detection and recovery systems in downstream switches, or, under loopback control, the locak receiving station. the hec error is accomplished by flipping bit 0 of the hec byte. 1, 0 r/w 0 = normal loopback control bit # 1 0 0 0 normal mode (receive from network) 1 1 phy loopback 1 1 line loopback
20 idt77v106l25 led driver and hec status/control register address: 0x03 bit type initial state function 7r 0 reserved 6 r/w 0 = enable disable receive hec checking (hec enable) checking when not set, the hec is calculated on first 4 bytes of received cell, and compared against the 5th byte. when set (= 1), the hec byte is not checked. 5 r/w 0 = enable disable transmit hec calculate & replace calculate when set, the 5th header byte of cells queued for transmit is not replaced with the hec calculated across & replace the first four replace bytes of that cell. 4, 3 r/w 00 = 1 cycle rxref pulse width selec t bit # 4 3 0 0 rxref active for 1 cycle of the recovered clock 0 1 rxref active for 2 cycle of the recovered clock 1 0 rxref active for 4 cycle of the recovered clock 1 1 rxref active for 8 cycle of the recovered clock 2 r 1 = empty transmit fifo status 1 = txfifo empty 0 = txfifo not empty 1r 1 txled status 0 = cell transmitted 1 = cell not transmitted 0r 1 rxled status 0 = cell received 1 = cell not received low byte counter register [7:0] address: 0x04 bit type initial state function [7:0] r 0x00 provides low-byte of counter value selected via the counter select register. high byte counter register [15:8] address: 0x05 bit type initial state function [7:0] r 0x00 provides high-byte of counter value selected via the counter select register. counter select register address: 0x06 bit type initial state function 7 ? 0 reserved 6 ? 0 reserved 5 ? 0 reserved 4 ? 0 reserved 3w 0 symbol error counter 2w 0 tx cell counter 1w 0 rx cell counter does not count hec errored cells. even when bit 6 of the master control register is cleared. 0w 0 receive hec error counter note: for proper operation, only one bit may be set in the counter selected register at any time.
21 idt77v106l25 interrupt mask register address: 0x07 bit type initial state function 7 ? 0 reserved 6 ? 0 reserved 5 r/w 0 = interrupt enable hec error cell 4 r/w 0 = interrupt enable short cell error 3 r/w 0 = interrupt enable transmit parity error 2 r/w 0 = interrupt enable receive signal condition change 1 r/w 0 = interrupt enable received cell symbol error 0 r/w 0 = interrupt enable receive fifo overflow enhanced control register address: 0x08 bit type initial state function 7 w 0 = not reset software reset 1 = reset. this bit is sell-clearing: it isn't necessary to write "0" to exit reset. 6 r/w 0 = osc transmit line clock (or loop timing mode) when set to 0, the osc input is used as the transmit like clock. when set to 1, the recovered receive clock is used as the transmit line clock. 5-0 r/w 0 reserved absolute maximum ratings symbol rating value unit note: when set to "1", these bits mask the corresponding interrupt pin ( int ). when set to "0", the interrupts are unmasked. these interrupts correspond to the interrupt status bits in the interrupt status registers. v term terminal voltage with respect to gnd -0.5 to +5.5 v t bias temperature under bias -55 to + 125 c t stg storage temperature -55 to +120 c i out dc output current 50 ma note: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress ra ting only and functional of the device at these or any other conditions above those indicated in the operational sections of this sp ecification is not implied. exposure to absolute maximum conditions for extended periods may affect reliability. recommended dc operating conditions symbol parameter min. typ. max unit vdd digital supply voltage 3.0 3.3 3.6 v gnd digital ground voltage 0 0 0 v vih input high voltage 2.0 ? 5.25 v vil input low voltage -0.3 ? 0.8 v avdo analog supply voltage 3.0 3.3 3.6 v agnd analog ground voltage 0 0 0 v vdif vdd - avdd -0.5 0 0.5 v
22 idt77v106l25 recommended operating temperature and supply voltage grade ambient gnd, agnd vdd, add temperature commercial 0 c to +70 c 0v 3.3v 0.3v industrial -40 c to +85 c 0v 3.3v 0.3v capacitance (ta = +25c, f = 1mhz) symbol parameter conditions max. unit c in input capacitance v in = 0v 10 pf c io i/o capacitance v out = 0v 10 pf symbol parameter test condition min. max. unit i li input leakage current gnd vin vdd -5 5 a i lo i/o (as input) leakage current gnd vin vdd -10 10 a v oh1 1 output logic "1" voltage ioh = -2ma, vdd = min 2.4 ? v v oh2 2 output logic "1" voltage ioh = -8ma, vdd = min 2.4 ? v v ol 1 output logic "0" voltage iol = 8ma, vdd = min ? 0.4 v v dd1 4,5 digital power supply current (vdd pins) osc = 32 mhz, all outputs unloaded ? 45 ma osc = 64 mhz, all outputs unloaded ? 80 ma v dd2 analog power supply current (avdd pins) osc = 32 mhz, all outputs unloaded ? 40 ma osc = 64 mhz, all outputs unloaded ? 55 ma dc electrical characteristics (all pins except txd+/- and rxd+/-) 1. for ad[7:0] pins only 2. for all output pins except ad[7:0], int and txd+/- 3. for all output pins except txd+/- 4. add 15ma when txd+/- is a driving mode. 5. total supply current is the sum of i dd 1 and i dd 2 symbol parameter test condition min. max. unit v oh output logic high voltage i oh = -20ma vdd - 0.5v ? v v ol output logic low voltage i ol = 20ma ? 0.5 v dc electrical characteristics (txd+/- and output pins only) symbol parameter min. typ max. unit v ir rxd+/- input voltage range 0 ? vdd v v ipp rxd+/- input peak-to-peak differential voltage 0.6 ? 2*vdd v v icm rxd+/- input common mode voltage 1.0 vdd/2 vdd-0.5 v dc electrical characteristics (rxd+/- and output pins only) note: differential signal amplitude is twice the amplitude of the individual signals that make up the differential signal.
23 idt77v106l25 symbol parameter min. typ unit t31 txclk frequency 0.2 50 mhz t32 txclk duty cycle (% of t31) 40 60 % t33 txdata[7:0], txparity setup time to txclk 4 ? ns t34 txdata[7:0], txparity hold time to txclk 1.5 ? ns t35 txsco, txen setup time to txclk 4 ? ns t36 txsoc, txen hold time to txclk 1.5 ? ns t37 txclk to txclav invalid (min) and valid (max) 2 10 ns t39 rxclk frequency 0.2 50 mhz t40 rxclk duty cycle (% of t39) 40 60 ns t41 rxen setup time to txclk 4 ? ns t42 rxen hold time to rxclk 1.5 ? ns t43 rxclk to rxclav invalid (min) and valid (max) 2 10 ns t44 rxclk to rxsoc high-z 2 10 ns t45 rxclk to rxsoc low-z (min) and valid (max) 2 10 ns t46 rxclk to rxdata, rxparity high-z 2 10 ns t47 rxclk to rxdata, rxparity low-z (min) and valid (max) 2 10 ns utopia bus timing parameters 77v106 drw 39 txen txclav txdata[7:0], txparity txsoc txclk t 33 t 37 t 35 t 34 t 31 t 32 t 36 octet 1 octet 2 77v106 drw 40 rxen rxclav rxdata[7:0], rxparity rxsoc rxclk t 41 t 39 t 40 t 43 t 42 t 45 t 47 t 46 t 44 t 47 t 45 high-z high-z high-z high-z figure 17. utopia transmit timing waveforms figure 18. utopia receive timing waveforms
24 idt77v106l25 name min max unit description tas 10 ? ns address setup to ale tcsrd 0 ? ns chip select to read enable tah 5 ? ns address hold to ale tapw 10 ? ns ale min pulse width ttria ? 0 ns address high-z to rd assert trdpw 20 ? ns min. rd pulse width tdh 0 ? ns data valid hold time tch 0 ? ns rd deassert to cs deassert trid ? 10 ns rd deassert to data high-z trd ? 18 ns read data access tar 5 ? ns ale low to start of read trdd 0 ? ns start of read to data low-z utility bus read cycle name min max unit description tapw 10 ? ns ale min pulse width tas 10 ? ns address set up to ale tah 5 ? ns address hold time to ale tcswr 0 ? ns cs assert to wr twrpw 20 ? n s min. wr pulse width tdws 20 ? ns write data set up tdwh 10 ? ns write data hold time tch 0 ? ns wr deassert to cs deassert taw 20 ? ns ale low to end of write utility bus write cycle 3505 drw 43 cs rd ale tah tas tapw tch trdd trdpw ad[7:0] (output) tdh trd ttrid tcsrd address data tar ad[7:0] (input) 3505 drw 44 cs wr ale ad[7:0] tah tas tapw tch tdwh tdws twrpw address data (input) taw tcswr figure 19. utility bus read cycle figure 20. utility bus write cycle
25 idt77v106l25 symbol parameter min. typ max unit tcyc osc cycle period (25.6 mbps) 30 31.25 33 ns (51.2 mbps) 15 15.625 16.5 ns tckh osc high time 40 ? 60 % tckl osc low time 40 ? 60 % tcc osc cycle to cycle period variation ? ? 1 % ttrh txref high time 35 ? ? ns ttrl txref low time 35 ? ? ns trspw minimum rst pulse width two osc cycles ? ? ? trrpw rxref pulse width (for default setting in register 0x03 0.9 1 1.1 receive and 25.6 mbps. can be programmed for multiples (31.25ns) data bit of this amount). period osc, txref and reset timing note: the minimum reset pulse width is either two rxclk cycles, two txclk cycles, or two osc cycles, whichever is greater (and applicable). 3505 drw 45 osc rst trspw txref ttrl ttrh tcyc tckh tckl rxref trrpw figure 21. osc, txref and reset timing input pulse levels gnd to 3.0v input rise/fall times 3ns input timing reference levels 1.5v output reference levels 1.5v output load see figure 22 ac test conditions figure 22 1.2k ? 30pf* 900 ? 3.3v d.u.t. figure 22. output load *includes jig and scope capacitances.
26 idt77v106l25 1 64 a1 a2 e b l 77v106 drw 49 a a1 a2 d d1 e e1 n e b b1 ccc ddd - .05 1.35 .17 .17 - - - .10 1.40 12.00 bsc 10.00 bsc 12.00 bsc 10.00 bsc 64 .50 bsc .22 .20 - - 1.60 .15 1.45 .27 .23 .08 .08 symbol min. nom. max. dimensions are in millimeters e1 e d1 d a package dimensions psc-4046 is a more comprehensive package outline drawing which is available from the packaging section of the idt web site.
27 corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 408-330-1552 santa clara, ca 95054 fax: 408-492-8674 email: telecomhelp@idt.com www.idt.com package idt nnnnn device type a power nnn speed a a process/ temp. range blank 25 speed in mb/s 77v106 25mbps atm phy 3.3v commercial (0c to +70c) 77v106 drw 50 l tf 64-lead tqfp (pp64-1) i industrial (-40c to +85c) . note: refer to the 77v406l25 device errata for an explanation of how to identify revisions and changes to revisions. revision history 4/29/99: preliminary. initial release. 3/23/2000: preliminary. various minor corrections. 1/4/2001: change from preliminary to final. txref , rxclav and txclav description update. rxref description updated, including led register and isc/ rxref timing. good signal bit improvement (y step). added dc electrical characteristics for rxd+/-. power supply current values updated. utility bus timing updated. utopia bus timing updated. change of r5 and r6 resistor value from 2.7k ? to 10k ? in table 3. master control register, bit 7 function change. 3/8/2001: changed package name from stqfp to tqfp. 3/28/2001: added rxref waveform and pulse width information in figure 21 and minor corrections. 9/21/2001: in table 1, under utopia signals: deleted "when in multi-phy mode xxclav is high impedance when xxen is high" in the signal description column for both rxclav and txclav signals. added loop timing feature screen. 7/11/2003: added note to table 3. 05/04/2004 1-27 update throughout datasheet.. ordering information

▲Up To Search▲

Price & Availability of IDT77V106L25TFI

	To Download IDT77V106L25TFI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .